1. Field of the Invention
The invention relates in general to a multiple-stage charge pump circuit, and more particularly to a multiple-stage charge pump circuit capable of recycling charges.
2. Description of the Related Art
In the technological age which changes with each passing day, a multiple-stage charge pump has been widely used in an occasion, in which a voltage signal having a voltage higher than a power voltage is used, and the high voltage may be needed to write or erase an electrically erasable programmable read only memory (EEPROM).
FIG. 1 (Prior Art) is a circuit diagram showing a conventional multiple-stage charge pump 100. Referring to FIG. 1, the multiple-stage charge pump 100 includes four stages of unit circuits 120 each including a diode D and a pumping capacitor C. Clock signals CK1 and CK2 having inverse phases respectively control the diodes in the odd-numbered stage of unit circuits and the even-numbered stage of unit circuits to turn on in alternate time periods so that charges in the pump capacitor of a previous-stage unit circuit charge the pump capacitor in the corresponding unit circuit. Thus, an output signal Vo having the level of voltage approximating to five times of the voltage (Vdd-Vd) can be generated by way of superimposing. Vd is the diode turn on voltage.
However, since each pump capacitor has to be repeatedly charged and discharged, the conventional multiple-stage charge pump circuit has the drawbacks of the high power consumption and the low power efficiency. Thus, it is an important subject of the invention to design a multiple-stage charge pump circuit having the low power consumption and the high power efficiency.